Course Sections:
1. What is a vector processor
2. RVV Basic Concept and CSRs
3. RVV load/store and arithmetic instructions
Course Sections:
1. Orientation
2. Getting Started
3. Resources
4. Module 1: System Verilog
5. Module 2: UVM Basics
6. Module 3: UVM Advanced
7. Module 4: SoC-IP Verification (Capstone)
This course will be used to consolidate the learning resources that our
trainees had been using for their processor design project. Future
trainees will find all learning materials, videos, worksheets etc at one
place.
Course Sections:
1. Resources
2. RISC V
3. Designing a Single Cycle processor
4. Project Submission
Course Sections:
1. Getting Started (Basics)
2. Modules & Classes
3. Arrays
4. Randomization
5. Threads & Interprocess Communication
6. Testdef / Enum
7. Time Regions / Simulation Cycles
8. TestBench Basics
9. Verifications Basics Live Session
10. Writing complete test bench
11. Case Study: Memory Model
12. Coverage
13. Test Planning
14. Grand Quiz
15. Final Project
Course Sections:
1. RISC-V Arch Test
1.2 Tasks
2. Setup Content
Course Sections:
1. C Language Features
2. Multi-Threading in C
3. Memory Management and File IO
4. Debugging
5. Data Structures and Algorithms
6. Grand Assessment
Course Sections:
1. Advance DFT
2. Advance PNR
3. Advance Sign off & SDA
4. Grand Assessment
Course Sections:
1. Setting up your computer for the Course
2. Python Fundamentals: Basic Construct (For Pre-Assessment)
3. Pre-Assessment
4. Advanced Function Techniques
5. Iterators and Generators
6. Classes
7. Regular Expressions (Regex)
8. Virtual Environments
9. Error Handling
10. Grand Assessment
Course Sections:
1. LLVM IR Structure and IR Instructions
2. Analysis Passes
3. Transformation Passes
4. Project